1. Field of the Invention
The present invention relates to a circuit design conversion apparatus for performing a testing for defects of an LSI.
2. Description of the Related Art
Generally, LSI is a sequential logic and comprises combinational logic 1 and register 2 as shown in FIG. 1. Combinational logic 1 comprises AND gate, OR gate, etc., and register 2 comprise flip-flops 2a, 2b and 2c. On the other hands, test of LSI can immediately be implemented by comparing, with an expected responses, responses which are obtained by applying simply to primary inputs test data which comprises a greater number of data as referred to as data pattern. However, combinational logic 1 is controlled by output signals of register 2 and register 2 is controlled by output signals of combinational logic 1. The outputs of register 2 is changed only when the clock pulses (not shown in FIG. 1) are applied thereto. Therefore, the test pattern is complex, much time-consuming in its generation and longer in the test time.
For this reason, a testing of LSI (sequential circuit) is performed by a testing of combinational logic 1 and by a testing of register 2, respectively. In this procedure, the test pattern for combinational logic 1 can be automatically generated by an algorithm. The testing of register 2 can be replaced by a testing of operation of the shift register, therefore it can easily performed. In order to test the combinational logic and the shift register, LSI is converted to a scannable circuit such that flip-flops 2a to 2c are replaced by scannable flip-flops 2A to 2C; flip-flops 2A to 2C have their terminals SI and SO for a scan path connected to each other; and flip-flop 2A is applied an external scan clock SC, while being applied a test pattern at a scan input terminal SI, to allow flip-flops 2A to 2C to be scanned with test pattern data. This method of converting a circuit design is called a "scan design conversion" and a designing of an LSI as a scannable one is called a "design for testability" whereby it is easier to test LSI of the sequential circuit.
A conventional circuit design conversion apparatus comprises, as shown in FIG. 3, hierarchy flattening unit 4 and circuit design conversion unit 5. Hierarchy flattening unit 4 flattens hierarchical circuit data 6 for hierarchically describing the connection of modules, that is, basic circuit units, to obtain non-hierarchically flat circuit data 7. Circuit design conversion unit 5 refers to conversion rule 8 registered with circuit modules allowing a circuit design conversion, that is, registered with scannable modules to be connected by a scan path, and converts a flat circuit into scan design data 7.
FIG. 4 shows an example of a hierarchy flatting. If an example is taken of a circuit (module) J, made up of modules A to I, as indicated by an upper section in FIG. 4, it is flattened into a lower section as shown in FIG. 4. A lowest level units (modules A to F) of the module corresponds to flip-flops in FIG. 2. If modules A, C and D are registered in rule 8, then a scan designed circuit obtained by scan design conversion unit 5 becomes a connection as indicated by the lower section in FIG. 4, where modules A, C and D are connected by a scan path. This circuit (module J) is scannable.
In order to prevent a waveform from being degraded during the transmission of a scan clock SC, it is necessary to insert a buffer into the scan clock system, though not shown in the Figure, upon the occurrence of the scan design conversion. If there is any asynchronous node ( node directly not controlled by external terminal) in the associated circuit, it is necessary to convert, to a synchronous node which can be directly and externally controlled by inserting a gate at that node.
Since the scan design conversion based on the "design for testability" is implemented after input hierarchical circuit connection data has once been converted by the hierarchy flattening unit to non-hierarchical circuit connection data, the following drawbacks have been encountered.
First, the aforementioned system is time-consuming in the flattening of such circuit data and greater in an amount of data to be processed, resulting in a greater time consumed in the scan design conversion and hence in a whole time involved.
When the circuit connection is to be modified, it is only necessary to remedy a single site if the hierarchical structure is maintained. In actual practice, however, it is necessary to modify many sites in the flattening of the hierarchical structure, resulting a situation which is not only complex but also time-consuming.
Furthermore, upon the flattening of the hierarchical structure, a new node name is generated, thus increasing an extra operation for examining a match between the new node name and an internal node before the flattening of the hierarchical structure. Many inconveniences will also arise from the flattening of the hierarchical structure even at a design stage following an examination step.